The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6920594 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 19, 2005

Filed:

May. 31, 2002
Applicants:

Hiroki Taniguchi, Kyoto, JP;

Masuko Taniguchi, Kyoto, JP;

Inventors:

Hiroki Taniguchi, Kyoto, JP;

Masuko Taniguchi, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R031/28 ;
U.S. Cl.
CPC ...
Abstract

A scan flip-flop circuit has a scan test data output terminal QT in addition to a Q terminal and a /Q terminal. To the QT terminal, the data that have been held in an internal data holding circuit is transferred via a tristate buffer that has been incorporated in advance. The drive capability of the tristate buffer is determined so that a propagation delay time is obtained and the scan test data outputted from the QT terminal is propagated to the scan test data input terminal DT of the next stage scan flip-flop circuit. Consequently, during scan testing, a sufficient delay is added to the output from the scan flip-flop circuit, and hold errors do not easily occur.


Find Patent Forward Citations

Taniguchi, Hiroki. (2005). Scan flip-flop circuit, logic macro, scan test circuit, and method for laying out the same (U.S. Patent No. 6920594). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6920594

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