The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
Jul. 19, 2002
Thomas B. Chadwick, Essex Junction, VT (US);
Tarl S. Gordon, Leander, TX (US);
Rahul K. Nadkarni, Colchester, VT (US);
Michael R. Ouellette, Westford, VT (US);
Jeremy Rowland, South Burlington, VT (US);
Thomas B. Chadwick, Essex Junction, VT (US);
Tarl S. Gordon, Leander, TX (US);
Rahul K. Nadkarni, Colchester, VT (US);
Michael R. Ouellette, Westford, VT (US);
Jeremy Rowland, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.