The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
Dec. 25, 2002
Ching-hsiang Hsu, Hsin-Chu, TW;
Chih-hsun Chu, Hsin-Chu, TW;
Ming-chou Ho, Hsin-Chu, TW;
Shih-jye Shen, Hsin-Chu, TW;
Ching-Hsiang Hsu, Hsin-Chu, TW;
Chih-Hsun Chu, Hsin-Chu, TW;
Ming-Chou Ho, Hsin-Chu, TW;
Shih-Jye Shen, Hsin-Chu, TW;
eMemory Technology Inc., Hsin-Chu, TW;
Abstract
A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first Pdoped drain region and a first Pdoped source region, the second PMOS transistor includes a single-poly select gate and a second Pdoped source region, and the first Pdoped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.