The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2005

Filed:

Nov. 25, 2003
Applicants:

Donald R. Preslar, Hillsborough, NJ (US);

Thomas J. Hayes, Hillsborough, NJ (US);

Inventors:

Donald R. Preslar, Hillsborough, NJ (US);

Thomas J. Hayes, Hillsborough, NJ (US);

Assignee:

Intersil Americas Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F001/10 ;
U.S. Cl.
CPC ...
Abstract

A controller for regulating a FET to operate as a pass device including input, output and gate nodes coupled to a current path input, a current path output and the gate of the FET, respectively, a controlled low current device, and an oscillating high gain regulation amplifier. The voltage source provides a regulation voltage level relative to the input node. The low current device is coupled to the gate node and has a control input. The amplifier has a first input coupled to the output node, a second input coupled to the voltage source, and an output coupled to the control input of the controlled low current device to regulate the FET. The amplifier oscillates while regulating a voltage between the input and output nodes to the regulation voltage level. The controlled low current device presents a high impedance to the gate node to prevent oscillations from disturbing regulation.


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