The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
Dec. 16, 2002
Applicants:
Shi-tron Lin, Taipei, TW;
Wei-fan Chen, Taichung, TW;
Inventors:
Shi-Tron Lin, Taipei, TW;
Wei-Fan Chen, Taichung, TW;
Assignee:
Winbond Electronics Corp., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/62 ; H02H009/00 ;
U.S. Cl.
CPC ...
Abstract
A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.