The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
Dec. 18, 2003
Sang-hyun OH, Ichon-shi, KR;
Kyu-hyun Bang, Ichon-shi, KR;
In-woo Jang, Ichon-shi, KR;
Jin-yong Seong, Ichon-shi, KR;
Jin-gu Kim, Ichon-shi, KR;
Song-hee Park, Ichon-shi, KR;
Young-ho Yang, Ichon-shi, KR;
Kye-nam Lee, Ichon-shi, KR;
Suk-kyoung Hong, Ichon-shi, KR;
Sang-Hyun Oh, Ichon-shi, KR;
Kyu-Hyun Bang, Ichon-shi, KR;
In-Woo Jang, Ichon-shi, KR;
Jin-Yong Seong, Ichon-shi, KR;
Jin-Gu Kim, Ichon-shi, KR;
Song-Hee Park, Ichon-shi, KR;
Young-Ho Yang, Ichon-shi, KR;
Kye-Nam Lee, Ichon-shi, KR;
Suk-Kyoung Hong, Ichon-shi, KR;
Hynix Semiconductor Inc., , KR;
Abstract
The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.