The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2005
Filed:
Jan. 08, 2003
Rob A. Rutenbar, Pittsburgh, PA (US);
Regis R. Colwell, Pittsburgh, PA (US);
Elias L. Fallon, Tempe, PA (US);
Rob A. Rutenbar, Pittsburgh, PA (US);
Regis R. Colwell, Pittsburgh, PA (US);
Elias L. Fallon, Tempe, PA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of each device. For each column and each row of cells having a plurality of device outlines contained completely therein, the position of one of the device outlines is determined and a constraint is established for each other device outline that expresses its position with respect to the position of the one device outline. A spacing constraint for each pair of adjacent device outlines is established that expresses a spacing therebetween. The foregoing constraints are solved simultaneously and a layout of the device outlines is generated in accordance with the solution.