The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2005

Filed:

Jul. 30, 2003
Applicants:

Jane Xin-leblanc, Santa Clara, CA (US);

Wai Lau, Taikoo Shing, HK;

Inventors:

Jane Xin-LeBlanc, Santa Clara, CA (US);

Wai Lau, Taikoo Shing, HK;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R023/12 ; H03L007/06 ;
U.S. Cl.
CPC ...
Abstract

A test circuit for connecting a high-impedance node to an external test point when a test signal is enabled. The test circuit comprises: a first transmission gate switch for coupling the high impedance node to a first internal node of the test circuit when the test signal is enabled, the first transmission gate switch comprising a first N-channel transistor having a drain coupled to the high impedance node, a gate coupled to a Logic 1 when the test signal is enabled, and a source coupled to the first internal node. The test circuit also comprises a second transmission gate switch capable of coupling the first internal node to the external test point when the test signal is enabled and a biasing circuit for generating a negative Vgs bias on the first N-channel transistor when the test signal is disabled to thereby reduce leakage current in the first N-channel transistor.


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