The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2005
Filed:
Apr. 15, 2004
Wagdi W. Abadeer, Jericho, VT (US);
Eric Adler, Jericho, VT (US);
Zhong-xiang He, Essex Junction, VT (US);
Bradley Orner, Colchester, VT (US);
Vidhya Ramachandran, Colchester, VT (US);
Barbara A. Waterhouse, Richmond, VT (US);
Michael Zierak, Essex Junction, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Eric Adler, Jericho, VT (US);
Zhong-Xiang He, Essex Junction, VT (US);
Bradley Orner, Colchester, VT (US);
Vidhya Ramachandran, Colchester, VT (US);
Barbara A. Waterhouse, Richmond, VT (US);
Michael Zierak, Essex Junction, VT (US);
International Busniess Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.