The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2005
Filed:
Mar. 19, 2001
Shao-yu Wang, Hsin-Chu, TW;
Chien-te Wu, Hsin-Chu, TW;
Jun-jyeh Hsiao, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the standard cells. Typically these standard cells are arranged in a row between two power buses. In this invention the standard cells are partitioned into first cells and second cells which can be combined to form the standard cell circuit. The first cells are arranged in a first row and the second cells are arranged in a second row. A first power bus is located above the first row of first cells and a second power bus is located below the second row of second cells. The first power bus and second power bus are electrically connected together. The first power bus supplies a first power supply voltage to the first cells and the second power bus supplies the first power supply voltage to the second cells. A third power bus is located between the first row of first cells and second row of second cells and supplies a second power supply voltage to the first and second cells. The layout can be accomplished automatically using a computer program.