The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6912612 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 28, 2005

Filed:

Feb. 05, 2003
Applicants:

Suvansh K. Kapur, Portland, OR (US);

Kai Cheng, Portland, OR (US);

Robert J. Hoogland, Portland, OR (US);

Inventors:

Suvansh K. Kapur, Portland, OR (US);

Kai Cheng, Portland, OR (US);

Robert J. Hoogland, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F013/36 ; G06F012/00 ; G01R031/08 ;
U.S. Cl.
CPC ...
Abstract

A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.


Find Patent Forward Citations

Kapur, Suvansh. (2005). Shared bypass bus structure (U.S. Patent No. 6912612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6912612

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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