The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2005
Filed:
Nov. 09, 2001
Xiaobao Wang, Santa Clara, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Nguyen, San Jose, CA (US);
Joseph Huang, San Jose, CA (US);
Bonnie Wang, Cupertino, CA (US);
Philip Pan, Freemont, CA (US);
Yan Chong, Stanford, CA (US);
IN Whan Kim, San Jose, CA (US);
Gopinath Rangan, Santa Clara, CA (US);
Tzung-chin Chang, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Nguyen, San Jose, CA (US);
Joseph Huang, San Jose, CA (US);
Bonnie Wang, Cupertino, CA (US);
Philip Pan, Freemont, CA (US);
Yan Chong, Stanford, CA (US);
In Whan Kim, San Jose, CA (US);
Gopinath Rangan, Santa Clara, CA (US);
Tzung-Chin Chang, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.