The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2005
Filed:
Apr. 16, 2003
Gregory W. Grynkewich, Gilbert, AZ (US);
Brian R. Butcher, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Kelly Kyler, Mesa, AZ (US);
Kenneth H. Smith, Chandler, AZ (US);
Clarence J. Tracy, Tempe, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Brian R. Butcher, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Kelly Kyler, Mesa, AZ (US);
Kenneth H. Smith, Chandler, AZ (US);
Clarence J. Tracy, Tempe, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.