The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6910195 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 21, 2005

Filed:

Feb. 05, 2003
Applicant:

Nataraj Akkiraju, Fremont, CA (US);

Inventor:

Nataraj Akkiraju, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F017/50 ;
U.S. Cl.
CPC ...
Abstract

A method and apparatus for inserting flip-flops in a circuit design between a driver and one or more receiver(s) comprising generating a candidate solution to assign the flip-flop at the node in the circuit, calculating a margin at the driver, calculating the margin at the receiver, and inserting the flip-flop at the node to simultaneously maximize the margin at the driver and the margin at the receiver. Furthermore, the method and apparatus determines whether to insert a second flip-flop at a second node in the circuit, and inserting the second flip-flop at the second node in the circuit such that a delay between the flip-flop and the second flip-flop is substantially equal to a clock period.


Find Patent Forward Citations

Akkiraju, Nataraj. (2005). Flip-flop insertion in a circuit design (U.S. Patent No. 6910195). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6910195

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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