The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2005

Filed:

Apr. 02, 2004
Applicants:

Chang-ki Jeon, Kyonggi-Do, KR;

Jong-jib Kim, Seoul, KR;

Young-suk Choi, Bucheon, KR;

Inventors:

Chang-Ki Jeon, Kyonggi-Do, KR;

Jong-Jib Kim, Seoul, KR;

Young-Suk Choi, Bucheon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/76 ;
U.S. Cl.
CPC ...
Abstract

A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrateformed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layerof p-type material and a second buried layerformed of n-type material. Layersandare arranged at the boundary between the semiconductor substrate and the drift region. A first well regionof p-type material contacts the first buried layern-type in a first portionof the drift region. A first source regionconductivity in a predetermined upper region of the first well region, a drain region formed of a material having second conductivity type impurities in a predetermined region of the drift region, the drain region being spaced a predetermined gap apart from the first well region, a third buried layer formed of a material having first conductivity type impurities in a second region of the drift region, the third buried layer being overlapped with a part of an upper portion of the first buried layer, a second well region formed of a material having first conductivity type impurities in the second region of the drift region, the second well region being overlapped with the third buried layer, a second source region formed of a material having second conductivity type impurities in a predetermined upper region of the second well region, a gate insulating layer formed in a first channel region inside the first well region and in a second channel region inside the second well region, a gate electrode formed on the gate insulating layer, a source electrode formed to be electrically connected to the first source region and the second source region, and a drain electrode formed to be electrically connected to the drain region.


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