Trench-capacitor dram cell having a folded gate conductor

Abstract

A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.