The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2005
Filed:
Sep. 15, 2003
Michael J. Rendon, Austin, TX (US);
John M. Grant, Austin, TX (US);
Ross E. Noble, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An insulating layer () is formed over a stack () of materials and a semiconductor substrate () and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers () are formed over the insulating layer (), the insulating layer () is etched, and heavily doped regions () are formed adjacent the spacers. The spacers () are then removed and extension regions () and optional halo regions () are formed by implanting through the insulating layer (). In one embodiment, the insulating layer () is in contact with the semiconductor substrate (). In one embodiment, the stack () is a gate stack including a gate dielectric (), a gate electrode (), and an optional capping layer (). The insulating layer () may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer () may be hafnium oxide.