The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2005

Filed:

Oct. 03, 2002
Applicants:

Ted Bruce, Villa Park, CA (US);

John A. Forthun, Glendora, CA (US);

Inventors:

Ted Bruce, Villa Park, CA (US);

John A. Forthun, Glendora, CA (US);

Assignee:

Staktek Group L.P., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/77 ;
U.S. Cl.
CPC ...
Abstract

A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.


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