The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2005
Filed:
Oct. 02, 2001
Maad A. Al-dabagh, Sunnyvale, CA (US);
Alexander Tetelbaum, Hayward, CA (US);
Maad A. Al-Dabagh, Sunnyvale, CA (US);
Alexander Tetelbaum, Hayward, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path for each cell pair. The total path delay of each identified longest path is calculated. Net delays are calculated for each cell pair. A crosstalk overhead delay is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to the calculated path delays. The circuit is redesigned to eliminate any path wherein the delay exceeds a maximum accepted delay. The stochastic model may be a tree-like structure derived from several completed integrated circuit designs, in particular from cell placement and wiring for each completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wiring factors.