The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2005

Filed:

Mar. 31, 2003
Applicants:

Ruiqi Tian, Pflugerville, TX (US);

Edward Outlaw Travis, Jr., Austin, TX (US);

Thomas Michael Brown, Austin, TX (US);

Inventors:

Ruiqi Tian, Pflugerville, TX (US);

Edward Outlaw Travis, Jr., Austin, TX (US);

Thomas Michael Brown, Austin, TX (US);

Assignees:

AMD, Inc., Sunnyvale, CA (US);

Motorola, Inc., Shaumberg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/311 ;
U.S. Cl.
CPC ...
Abstract

In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.


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