The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Mar. 17, 2003
Jawahar Jain, Santa Clara, CA (US);
Amit Narayan, Redwood City, CA (US);
Subramanian K. Iyer, Austin, TX (US);
Debashis Sahoo, Stanford, CA (US);
Jawahar Jain, Santa Clara, CA (US);
Amit Narayan, Redwood City, CA (US);
Subramanian K. Iyer, Austin, TX (US);
Debashis Sahoo, Stanford, CA (US);
Fujitsu Limited, Kawasaki, JP;
Abstract
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are then executed using the information in order to generate a first set of states at a first depth associated with a sub-space within the target circuit. Bounded model checking may be executed using the first set of states in order to generate a second set of states at a second depth associated with the sub-space within the target circuit. The first set of states may be used as a basis for the second set of states such that the second depth is greater than the first depth.