The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Aug. 09, 2002
Chun Kit NG, Portland, OR (US);
Kenneth S. Mcelvain, Los Altos, CA (US);
Chun Kit Ng, Portland, OR (US);
Kenneth S. McElvain, Los Altos, CA (US);
Synplicity, Inc., Sunnyvale, CA (US);
Abstract
A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).