The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2005
Filed:
Dec. 23, 2003
Nhon Quach, San Jose, CA (US);
John Crawford, Los Gatos, CA (US);
Greg S. Mathews, Santa Clara, CA (US);
Edward Grochowski, San Jose, CA (US);
Chakravarthy Kosaraju, Sunnyvale, CA (US);
Nhon Quach, San Jose, CA (US);
John Crawford, Los Gatos, CA (US);
Greg S. Mathews, Santa Clara, CA (US);
Edward Grochowski, San Jose, CA (US);
Chakravarthy Kosaraju, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.