The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2005

Filed:

Jul. 14, 2003
Applicants:

Jason Cheng, Fremont, CA (US);

Cyrus Tsui, Los Altos Hills, CA (US);

Satwant Singh, Fremont, CA (US);

Albert Chan, Palo Alto, CA (US);

Ju Shen, Saratoga, CA (US);

Clement Lee, Portland, OR (US);

Inventors:

Jason Cheng, Fremont, CA (US);

Cyrus Tsui, Los Altos Hills, CA (US);

Satwant Singh, Fremont, CA (US);

Albert Chan, Palo Alto, CA (US);

Ju Shen, Saratoga, CA (US);

Clement Lee, Portland, OR (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/177 ;
U.S. Cl.
CPC ...
Abstract

A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.


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