The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Oct. 15, 2002
Applicants:

Paul R. Dougherty, Hillsboro, OR (US);

Srirama Chandra, Beaverton, OR (US);

Hans W. Klein, Danville, CA (US);

Inventors:

Paul R. Dougherty, Hillsboro, OR (US);

Srirama Chandra, Beaverton, OR (US);

Hans W. Klein, Danville, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/00 ; G06F017/50 ; G06F001/26 ;
U.S. Cl.
CPC ...
Abstract

A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user constructs a program, wherein the program comprises instructions defining inputs, outputs, and conditional branching for an abstract state sequencer that implements the desired circuit behavior. The programming technique then translates the states and resources for the abstract state sequencer into HDL source code, which in turn may be translated into a programming bit pattern for the PLD.


Find Patent Forward Citations

Quick Actions:

Dougherty, Paul. (2005). Power sequence controller programming technique (U.S. Patent No. 6901572). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6901572

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…