The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Oct. 24, 2001
Applicants:

Joerg Huth, Unterfoehring, DE;

Andreas Hils, Unterhaching, DE;

Inventors:

Joerg Huth, Unterfoehring, DE;

Andreas Hils, Unterhaching, DE;

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R031/28 ;
U.S. Cl.
CPC ...
Abstract

The invention relates to an integrated circuit including a hard-core and a peripheral circuit. The hard-core and the peripheral circuit each include respective registers, which are couplable for scan chain testing by respective scan chain paths within the core and within the peripheral circuit. In order to avoid timing problems between the two scan chain paths, a lock-up latch is provided within the hard-core. The lock-up latch has an input coupled to the last register in the scan chain path within the hard-core, and an output coupled to the first register in the scan chain path in the peripheral circuit. The lock-up latch forms part of the hard-core and is clocked by the same clock signal as the last register in the hard-core scan chain path.


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