The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Sep. 02, 2003
Applicant:

Luis J. Briones, Chandler, AZ (US);

Inventor:

Luis J. Briones, Chandler, AZ (US);

Assignee:

Standard Microsystems Corporation, Hauppauge, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L007/06 ;
U.S. Cl.
CPC ...
Abstract

In one set of embodiments, the invention comprises a system and method for automatically trimming the center frequency of a VCO in a PLL. The trimming may be performed by a digitally controlled trimming circuit, which may be operated to modify a gain of the VCO and may be used as part of a clock recovery architecture or as part of a high-end PLL. It may also be used by itself in low-end PLLs. In one embodiment, a second loop based solely on the frequency difference between a reference frequency and a divided output frequency of the VCO is introduced into the PLL loop. This frequency loop may be optimized by the inclusion of a gain control stage, which may lower the locking time. A control module may also be introduced to delay the deployment of the phase detector until the frequency loop has fully converged, that is until trimming has been completed, thus preventing the two loops from interfering with each other and compromising each other's performance.


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