The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2005
Filed:
Dec. 04, 2002
Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement
Applicants:
Franz Hofmann, München, DE;
R. Johannes Luyken, München, DE;
Wolfgang Rösner, Ottobrunn, DE;
Inventors:
Assignee:
Infineon Technologies AG, , DE;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L027/108 ;
U.S. Cl.
CPC ...
Abstract
The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has a monocrystalline substrate, a highly doped region in the substrate and a metallically conductive structure in the highly doped region, a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.
Hofmann, Franz. (2005). Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement (U.S. Patent No. 6900495). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6900495
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile