The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6898781 B1

PDF
Full Text
Expired
Date of Patent:
May. 24, 2005

Filed:

Jul. 30, 2003
Applicants:

Vivek K. Singh, Portland, OR (US);

John Ernst Bjorkholm, Pleasanton, CA (US);

Francisco A. Leon, Palo Alto, CA (US);

Inventors:

Vivek K. Singh, Portland, OR (US);

John Ernst Bjorkholm, Pleasanton, CA (US);

Francisco A. Leon, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F017/50 ; G06F019/00 ; G06F017/10 ;
U.S. Cl.
CPC ...
Abstract

A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.


Find Patent Forward Citations

Singh, Vivek. (2005). Method for modifying a chip layout to minimize within-die cd variations caused by flare variations in euv lithography (U.S. Patent No. 6898781). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6898781

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