The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2005

Filed:

Aug. 11, 2003
Applicants:

Hebbalalu S. Ramagopal, Austin, TX (US);

Michael Allen, Austin, TX (US);

Jose Fridman, Brookline, MA (US);

Marc Hoffman, Mansfield, MA (US);

Inventors:

Hebbalalu S. Ramagopal, Austin, TX (US);

Michael Allen, Austin, TX (US);

Jose Fridman, Brookline, MA (US);

Marc Hoffman, Mansfield, MA (US);

Assignees:

Intel Corporation, Santa Clara, CA (US);

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F012/10 ;
U.S. Cl.
CPC ...
Abstract

An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.


Find Patent Forward Citations

Ramagopal, Hebbalalu. (2005). Multi-tiered memory bank having different data buffer sizes with a programmable bank select (U.S. Patent No. 6898690). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6898690

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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