The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2005

Filed:

Feb. 05, 2001
Applicants:

Dominique Drouin, Deauville, CA;

Eric Lavallée, Sherbrooke, CA;

Jacques Beauvais, Sherbrooke, CA;

Inventors:

Dominique Drouin, Deauville, CA;

Eric Lavallée, Sherbrooke, CA;

Jacques Beauvais, Sherbrooke, CA;

Assignee:

Quantiscript, Inc., Sherbrooke, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/44 ;
U.S. Cl.
CPC ...
Abstract

A lithography method for fabricating structures of etch-resistant metal-semiconductor compound on a substrate with sub-micrometer scale resolutions is described. Superposed layers of metal and semiconductor capable of reacting with each other to form etch-resistant metal/semiconductor compound are deposited on the substrate. Radiation from a X-ray/EUV source propagates through a patterned X-ray transparent/EUV reflective mask and is projected on the superposed metal and semiconductor layers. The X-ray transparent mask includes X-ray absorbing patterns imparted to the X-ray radiation while the EUV reflective mask includes EUV absorbing patterns also imparted to the EUV radiation. The energy of X-ray/EUV photons is absorbed locally by the metal and semiconductor layers. Absorption of this energy induces a reaction between the two layers responsible for the formation of etch-resistant metal/semiconductor compound with structures corresponding to the patterns imparted to the radiation by the X-ray/EUV mask. The metal layer is subsequently etched using selective plasma or wet etching, leaving the structures of etch-resistant metal/semiconductor compound intact. The semiconductor layer may also be etched using selective plasma or wet etching, also leaving the structures of etch-resistant metal/semiconductor compound intact. The underlying layers of the substrate may also be partially or completely etched away using selective plasma or wet etching. Again, the structures of etch resistant metal/semiconductor compound protects the substrate against etching whereby these structures form corresponding patterns in the underlying layers of the substrate.


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