The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2005
Filed:
Jul. 14, 2003
Applicants:
Sheng-wei Yang, Tainan Hsien, TW;
Cheng-chih Huang, Taipei Hsien, TW;
Chien-mao Liao, Taipei Hsien, TW;
Inventors:
Sheng-Wei Yang, Tainan Hsien, TW;
Cheng-Chih Huang, Taipei Hsien, TW;
Chien-Mao Liao, Taipei Hsien, TW;
Assignee:
Nanya Technology Corp., Tao-Yuan Hsien, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8242 ; H01L021/20 ;
U.S. Cl.
CPC ...
Abstract
The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.