The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Aug. 27, 2002
John G Rohrbaugh, Ft Collins, CO (US);
Jeff Rearick, Ft Collins, CO (US);
Daryl H Allred, Ft Collins, CO (US);
John G Rohrbaugh, Ft Collins, CO (US);
Jeff Rearick, Ft Collins, CO (US);
Daryl H Allred, Ft Collins, CO (US);
Agilent Technologies, Inc., Palo Alto, CA (US);
Abstract
A method and apparatus of carrying out a computer assisted analysis function on a hierarchical circuit model. The method is carried out by inputting the hierarchical circuit model, specifying at least one circuit block within the hierarchy as a target of the function on the target block, and simplifying the hierarchical circuit model by deleting circuit blocks not affecting the analysis function, to produce a simplified hierarchical circuit model. A computer assisted analysis function can then be carried out on the simplified hierarchical circuit model. The model is simplified by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block is a circuit block desired in the computer assisted analysis and if so keeping the circuit block as part of the simplified hierarchical circuit model; and by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block comprises a parent circuit block containing a child circuit block desired in the computer assisted analysis and if so keeping the parent circuit block as part of the simplified hierarchical circuit model.