The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Jun. 25, 2003
Koichiro Ishibashi, Warabi, JP;
Shoji Shukuri, Koganei, JP;
Kazumasa Yanagisawa, Kokubunji, JP;
Junichi Nishimoto, Hachiouji, JP;
Masanao Yamaoka, Hachiouji, JP;
Masakazu Aoki, Tokorozawa, JP;
Koichiro Ishibashi, Warabi, JP;
Shoji Shukuri, Koganei, JP;
Kazumasa Yanagisawa, Kokubunji, JP;
Junichi Nishimoto, Hachiouji, JP;
Masanao Yamaoka, Hachiouji, JP;
Masakazu Aoki, Tokorozawa, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.