The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Sep. 05, 2002
Mehran Sedigh, Campbell, CA (US);
Saurabu Dutta Chowdhury, Belmont, CA (US);
Mehran Sedigh, Campbell, CA (US);
Saurabu Dutta Chowdhury, Belmont, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A system and method is provided herein to fabricate openings in a semiconductor topography using feed forward control of etch process parameters. In one embodiment, a method includes measuring one or more dimensional features of a semiconductor topography to obtain pre-etch values. The method also includes determining a statistical result of the pre-etch values and adjusting one or more processing parameters if the statistical result is less than a target value. Subsequently, the method includes etching the semiconductor topography based upon the statistical result to form one or more openings in the semiconductor topography. As such, the system and method described herein fabricates openings using feed forward control of the etch process parameters to compensate for structural variations within semiconductor topographies that may exist between wafer-to-wafer and/or between lot-to-lot. In this manner, the system and method advantageously fabricates openings having profiles and dimensions, which exhibit little to no deviation from a design specification.