The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Oct. 07, 2003
Yu-ren Wang, Tainan, TW;
Chun-yi Lee, Hsinchu, TW;
Yu-kun Chen, Hsinchu, TW;
Neng-hui Yang, Hsinchu, TW;
Yu-Ren Wang, Tainan, TW;
Chun-Yi Lee, Hsinchu, TW;
Yu-Kun Chen, Hsinchu, TW;
Neng-Hui Yang, Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.