The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
May. 30, 2003
Toshiharu Furukawa, Essex Junction, VT (US);
Mark C. Hakey, Fairfax, VT (US);
Steven J. Holmes, Milton, VT (US);
David V. Horak, Essex Junction, VT (US);
William H. MA, Fishkill, NY (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Mark C. Hakey, Fairfax, VT (US);
Steven J. Holmes, Milton, VT (US);
David V. Horak, Essex Junction, VT (US);
William H. Ma, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile