The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2005

Filed:

Mar. 19, 2003
Applicants:

Joachim Krumrey, München, DE;

Franz Hirler, Isen, DE;

Ralf Henninger, München, DE;

Martin Pölzl, Ossiach, AT;

Walter Rieger, Arnoldstein, AT;

Inventors:

Joachim Krumrey, München, DE;

Franz Hirler, Isen, DE;

Ralf Henninger, München, DE;

Martin Pölzl, Ossiach, AT;

Walter Rieger, Arnoldstein, AT;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/76 ;
U.S. Cl.
CPC ...
Abstract

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.


Find Patent Forward Citations

Krumrey, Joachim. (2005). Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell (U.S. Patent No. 6891223). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6891223

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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