The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Sep. 12, 2002
Shigeru Kimura, Tokyo, JP;
Takahiko Watanabe, Tokyo, JP;
Tae Yoshikawa, Tokyo, JP;
Hiroyuki Uchida, Izumi, JP;
Shusaku Kido, Izumi, JP;
Shinichi Nakata, Izumi, JP;
Tsutomu Hamada, Izumi, JP;
Hisanobu Shimodouzono, Izumi, JP;
Satoshi Doi, Izumi, JP;
Toshihiko Harano, Izumi, JP;
Akitoshi Maeda, Tokyo, JP;
Satoshi Ihida, Tokyo, JP;
Hiroaki Tanaka, Tokyo, JP;
Takasuke Hayase, Tokyo, JP;
Shouichi Kuroha, Tokyo, JP;
Hirofumi Ihara, Tokyo, JP;
Kazushige Takechi, Tokyo, JP;
Shigeru Kimura, Tokyo, JP;
Takahiko Watanabe, Tokyo, JP;
Tae Yoshikawa, Tokyo, JP;
Hiroyuki Uchida, Izumi, JP;
Shusaku Kido, Izumi, JP;
Shinichi Nakata, Izumi, JP;
Tsutomu Hamada, Izumi, JP;
Hisanobu Shimodouzono, Izumi, JP;
Satoshi Doi, Izumi, JP;
Toshihiko Harano, Izumi, JP;
Akitoshi Maeda, Tokyo, JP;
Satoshi Ihida, Tokyo, JP;
Hiroaki Tanaka, Tokyo, JP;
Takasuke Hayase, Tokyo, JP;
Shouichi Kuroha, Tokyo, JP;
Hirofumi Ihara, Tokyo, JP;
Kazushige Takechi, Tokyo, JP;
NEC LCD Technologies, LTD., , JP;
Abstract
An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and namorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the namorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.