The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Jul. 06, 2004
Gregory W. Grynkewich, Gilbert, AZ (US);
Mark Deherrera, Tempe, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Clarence J. Tracy, Tempe, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Mark Deherrera, Tempe, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Clarence J. Tracy, Tempe, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.