The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2005
Filed:
Jun. 01, 2001
Hiromi Watanabe, Mitaka, JP;
Takashi Nakamoto, Tama, JP;
Hiroshi Hatae, Toda, JP;
Junko Haruta, Kodaira, JP;
Masaru Hase, Kokubunji, JP;
Kenichi Iwata, Higashimurayama, JP;
Hiroshi Yamada, Higashimurayama, JP;
Yutaka Okada, Tokyo, JP;
Hiromi Watanabe, Mitaka, JP;
Takashi Nakamoto, Tama, JP;
Hiroshi Hatae, Toda, JP;
Junko Haruta, Kodaira, JP;
Masaru Hase, Kokubunji, JP;
Kenichi Iwata, Higashimurayama, JP;
Hiroshi Yamada, Higashimurayama, JP;
Yutaka Okada, Tokyo, JP;
Renesas Technology Corporation., Tokyo, JP;
Abstract
A signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. A local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits and determines which of the second local bus, first local bus, and system bus will be connected to the local memory bus.