Lead frame chip scale package

Abstract

In one aspect of the invention, a lead frame panel suitable for use in packaging an array of integrated circuits is described. The lead frame panel includes a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediately adjacent device areas separated only by the tie bars. Each device area is suitable for use in an independent integrated circuit package and includes a die attach pad and a plurality of conductive contacts. In another aspect of the invention, a panel assembly suitable for use in simultaneously packaging a multiplicity of integrated circuits is described. The panel assembly includes a lead frame panel formed from a conductive sheet. The lead frame panel is patterned to define at least one two dimensional array of adjacent device areas. Each device area is suitable for use as part of an independent integrated circuit package and including a die and a plurality of contacts positioned around and electrically connected to the die. A molded cap is also provided that substantially uniformly covers a two dimensional array of adjacent device areas while leaving bottom surfaces of the conductive contacts exposed to facilitate electrical connection to external components. The encapsulation material that forms the molded cap is exposed at a bottom surface of the panel of integrated circuits to physically isolate the contacts.