The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6885961 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 26, 2005

Filed:

Feb. 28, 2002
Applicants:

Peter Breger, Calabasas, CA (US);

Grady Borders, West Hills, CA (US);

Inventors:

Peter Breger, Calabasas, CA (US);

Grady Borders, West Hills, CA (US);

Assignee:

Teradyne, Inc., Boston, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F011/26 ;
U.S. Cl.
CPC ...
Abstract

A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.


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