The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6885608 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 26, 2005

Filed:

Oct. 10, 2002
Applicant:

Hideo Nagano, Tokyo, JP;

Inventor:

Hideo Nagano, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C008/00 ;
U.S. Cl.
CPC ...
Abstract

A memory cell includes first and second NMOS transistors and a capacitor that forms a storage node. During write operation, the first transistor is turned ON by a write address select circuit and a data bit is written on the storage node. During read operation, read bit lines are precharged, the second transistor is turned ON by a read address select circuit and the data bit held on the storage node is read. Data is read out without destruction when the storage node is at high logical level. However, if it has a low logical level, then a sense amplifier circuit outputs a low level and a refresh circuit writes a low level on the storage node.


Find Patent Forward Citations

Nagano, Hideo. (2005). Multi-port memory circuit (U.S. Patent No. 6885608). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6885608

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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