The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2005
Filed:
Mar. 11, 2002
Brian D. Emberling, San Mateo, CA (US);
Ewa M. Kubalska, San Jose, CA (US);
Steve Kurihara, Palo Alto, CA (US);
Anthony S. Ramirez, Sunnyvale, CA (US);
Andre J. Gaytan, Pleasanton, CA (US);
Brian D. Emberling, San Mateo, CA (US);
Ewa M. Kubalska, San Jose, CA (US);
Steve Kurihara, Palo Alto, CA (US);
Anthony S. Ramirez, Sunnyvale, CA (US);
Andre J. Gaytan, Pleasanton, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.