The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2005
Filed:
Oct. 11, 2000
Serge F. Fruhauf, Saratoga, CA (US);
Alain Christophe Pomet, Austin, TX (US);
Robert Antoine Leydier, La Londe las Maurez, FR;
Serge F. Fruhauf, Saratoga, CA (US);
Alain Christophe Pomet, Austin, TX (US);
Robert Antoine Leydier, La Londe las Maurez, FR;
STMicroelectronics, Inc., Carrollton, TX (US);
Schlumberger Malco, Inc., Owings Mills, MD (US);
Abstract
A multi-mode IC is provided for operating in a first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The multi-mode IC is preferably in a smart card and includes a microprocessor and an external interface. The external interface comprises a voltage supply pad, a ground pad, a first set of pads for the first mode, and 2 second set of pads for the second mode. The first set of pads preferably include a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and may also include a variable supply voltage pad in accordance with the ISO 7816 protocol. The IC further includes a mode configuration circuit for detecting a mode condition on one pad of the first set of pads, and configuring the IC in the ISO mode or the non-ISO mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.