The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2005

Filed:

Mar. 08, 2004
Applicant:

Shiao-shien Chen, Hsin-Chu, CN;

Inventor:

Shiao-Shien Chen, Hsin-Chu, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/62 ;
U.S. Cl.
CPC ...
Abstract

An ESD protection device having reduced trigger voltage is disclosed. A first MOS transistor includes a first gate, a first heavily doped region at one side of the first gate, and a second heavily doped region at the other side of the first gate. A second MOS transistor is laterally disposed in proximity to the first MOS transistor. The second MOS transistor includes a second gate, a third heavily doped region at one side of the second gate, and a fourth heavily doped region at the other side of the second gate. The floating gate MOS transistor is located between the first and second MOS transistors. A floating gate MOS transistor is serially connected to the first MOS transistor via the second heavily doped region and is serially connected to the second MOS transistor via the third heavily doped region.


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