The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2005
Filed:
Jul. 01, 2003
Eugene A. Fitzgerald, Windham, NH (US);
Nicole Gerrish, Cambridge, MA (US);
Eugene A. Fitzgerald, Windham, NH (US);
Nicole Gerrish, Cambridge, MA (US);
AmberWave Systems Corporation, Salem, NH (US);
Abstract
A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed SiGelayer on the Si substrate, and a strained surface layer on said relaxed SiGelayer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed SiGelayer on the Si substrate, and a strained layer on the relaxed SiGelayer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.