The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Oct. 16, 2002
Qian Cui, Cupertino, CA (US);
Robert W. Davis, Fort Collins, CO (US);
Sandeep Bhutani, Sunnyvale, CA (US);
Payman Zarkesh-ha, Fremont, CA (US);
John D. Corbeil, Jr., Fort Collins, CO (US);
Prabhakaran Krishnamurthy, San Jose, CA (US);
Qian Cui, Cupertino, CA (US);
Robert W. Davis, Fort Collins, CO (US);
Sandeep Bhutani, Sunnyvale, CA (US);
Payman Zarkesh-Ha, Fremont, CA (US);
John D. Corbeil, Jr., Fort Collins, CO (US);
Prabhakaran Krishnamurthy, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.