The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2005

Filed:

Dec. 29, 2003
Applicant:

Robert A. Jacobs, Portland, OR (US);

Inventor:

Robert A. Jacobs, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F012/00 ;
U.S. Cl.
CPC ...
Abstract

A NOR-gate architecture memory with an erase and write time table. The memory processor creates an erase and write time table in a table block. The table contains the most recent times for erase and write operations for each data block in the memory. When a storage operation is initiated, the processor accesses the table and estimates the amount of time it will take to perform the data storage operation and then communicates that back to a host computer. Each data storage operation results in a new table being created that is written into the data block. To save erase and write operations for the table block, the new table is written directly after the most recent table unless there is not enough space. An erase and write operation is only performed on the table block if there is not enough space for the new table.


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